izvorni znanstveni rad
Frequency table computation is a common procedure used in variety of machine learning algorithms. In this paper we present a parallelized kernel for computing frequency tables. The kernel is targeted for dataflow architecture implemented on field programmable gate array (FPGA). Its performance was evaluated against a parallelized software implementation running on a 6-core CPU. The kernel with six concurrent input data streams running on 300 MHz achieved speedup of up to 6.26×, compared to 6 threaded software implementation running on 3.2 GHz CPU.
frequency table; dataflow; field programmable gate arrays; decision tree learning
Razvojem virtualizacijskih tehnologija raste kompleksnost IT sustava, dok korisnici istovremeno zahtijevaju brži pristup resursima, napredne integracije i jednostavnost korištenja. Jedno od ključnih rješenja za ove izazove primjena je…
Ovaj rad istražuje i uspoređuje mogućnosti prosljeđivanja grafičkih kartica na Hyper-V i KVM hipervizorima prema virtualnim strojevima, detaljno opisujući metode, postupke i razlike u arhitekturi koje utječu na…
The ever-growing usage and adaptation of HTTP/3 in web traffic leverages Quick UDP Internet Connections (QUIC) as a transport protocol. QUIC is widely recognized for reduced latency, enhanced…
