izvorni znanstveni rad
General-purpose processors are often unable to effectively exploit the parallelism inherent to the software code. In such cases, additional hardware accelerators are needed to enable meeting the performance goals. To shorten time to market and enable meeting design constraints, designers today use special tools and technologies like the No-Instruction-Set Computer (NISC) to automatically generate custom accelerators. However, it is often difficult to integrate these accelerators into general-purpose processor systems and use them from the main processor’ s software. In this paper we present a simple and efficient method for using the NISC processor as a loosely-coupled coprocessor. To enable communication with the NISC processor, a simple set of coprocessor services exposed to the application programmer is defined. A hardware solution based on standard SoC bus architectures for implementing these services is described. Using a standard SoC bus interface enables simple integration of the NISC design flow into an existing design flow. A practical implementation of the NISC coprocessor WISHBONE interface was realized and tested in a system based on a WISHBONE-compatible general-purpose soft processor.
Wishbone; NISC; hradware accelerator; System-On-Chip
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