Top level design contribution to the design process

Software package VisualSIM is used for modeling and simulation of electronic systems at the top level. Using it, designer can perform architectural analysis of algorithms, components, software instructions and hardware/ software partitioning. VisualSim Architect, as a commercial version of the research project at University of California, Berkeley, has many attributes that make it applicable for enhancing the education process, hands-on student experience and projects. It has a powerful graphical user interface and can be used for performance trade-off analyses using indicators such as bandwidth utilization, application response time and buffer requirements. In the article we analyze system level modeling challenges and consider the tool from the applicability in education process and creativity point of view.