Shifter Designs for ASIC’s

This paper presents four versions of 32 bit shifter designes that can be used in ASICs, namely: barrel shifter and logarithmic shifter, each implemented with pass transistors and transmission gates. The circuits are designed in standard MOSIS scalable CMOS n-well technology with the 0.8 um minimal feature size fabrication process. The design procedure is thoroughly explained. The designs are logically and electrically simulated. They are compared according to the funcionality, wafer area, number of transistors, delay and power dissipation. The usage and optimization guidelines are given.