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Function-level Performance Estimation for Heterogeneous MPSoC Platforms

izvorni znanstveni rad

izvorni znanstveni rad

Function-level Performance Estimation for Heterogeneous MPSoC Platforms

Vrsta prilog sa skupa (u zborniku)
Tip izvorni znanstveni rad
Godina 2016
Nadređena publikacija ZINC 2016
Stranice str. 37-40
DOI 10.1109/ZINC.2016.7513650
Status objavljeno

Sažetak

Main challenge of system-level design is fast and accurate performance estimation on heterogeneous multiprocessor system-on-chip (MPSoC) platforms in early design stages. In this paper the authors present a design flow of a novel framework for automated early high- level software performance estimation based on source code analysis using elementary operation concept. The tools implemented within the framework support performance evaluation by application C code intermediate representation analysis and production of profiling data per single line of code instruction. The concept of elementary operation usage in gaining the appropriate application profiling is tested on two processor cores as representatives of different processing elements often used inside MPSoC platforms. Preliminary results demonstrate the ability to provide fast and efficient design space exploration with high accuracy of performance estimation.

Ključne riječi

Embedded Computer Systems ; Heterogeneous Computing ; FPGA ; System-level design ; Design Space Exploration ; Performance Estimation