izvorni znanstveni rad
Frequency table computation is a key step in decision tree learning algorithms. In this paper we present a novel implementation targeted for dataflow architecture implemented on field programmable gate array (FPGA). Consistent with dataflow model of computation, the kernel views input dataset as synchronous streams of attributes and class values. The kernel was benchmarked using key functions from C4.5 program for decision tree learning. For large datasets with many attributes – over 100, 000 items, and over 60 attributes – the realized kernel, clocked at 333 MHz, outperforms the software implementation running on CPU clocked at 3.2 GHz.
dataflow; decision tree learning; field programmable; frequency table; gate arrays
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