Barrel Shifter Design and Simulations

The paper presents 32-bit barrel shifter implementation for use in ASICs. The barrel shifter is realized using pass transistors and combination of combinatorial and dynamic logic. It is adapted for usage in typical data path found in modern processors or ASICs. The circuit is designed in standard MOSIS CMOS n-well technology and implemented in 0.8 *m process. The design is logically verified and simulated to establish computational delay and dissipated power. The usage and optimization guidelines are given.
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