An Approach to the Determination of the Reliability of Semiconductor Memory Systems

Abstract: The approach for the increase and determination of the memory system reliability is presented. The paper starts with the development of the reliability model of the basic memory array. It is upgraded to the models suitable for the analysls of more complex systems imploying techniques such as hardware redundancies, error correcting codes, software error correcting algorithms. The models incorporate also the effects of faults masked by data. The developed models are particularly useful for the estimation of the semiconductor memories reliability. The results suggest that the erasure correction method render the optimal reliability.