1 um n-Well CMOS Technology Design

The fabrication process of the 1 μm CMOS technology for digital VLSI circuits with supply voltages of 3 and 5 V is analyzed and designed. Basic process features are the LOCOS isolation, the n-well, the boron implantation into the channels for threshold voltage control, and the n+ polysilicon gates. Electrical characteristics of MOSFET can be adjusted by varying the parameters of the implantation steps. Process and device simulations result in the threshold voltages UTHn = −UTHp = 0.73 V. For symmetrical output characteristics the ratio of p- and n-MOSFET channel width Wp/Wn= 2 is needed. The process can be easily extended to the fabrication of both nMOS and CMOS circuits on the same chip by introduction of minor modifications.