izvorni znanstveni rad
Frequency table computation is a common procedure used in variety of machine learning algorithms. In this paper we present a parallelized kernel for computing frequency tables. The kernel is targeted for dataflow architecture implemented on field programmable gate array (FPGA). Its performance was evaluated against a parallelized software implementation running on a 6-core CPU. The kernel with six concurrent input data streams running on 300 MHz achieved speedup of up to 6.26×, compared to 6 threaded software implementation running on 3.2 GHz CPU.
frequency table; dataflow; field programmable gate arrays; decision tree learning
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