izvorni znanstveni rad
Nanometer technology and high chip frequency place high demand on the EDA (Electronic Design Automation) tools to reliably and efficientlly find design problems in post-layout verification process. The only way to tackle designs with over billion transistors on a single chip is to use the knowledge and skill of highly experienced engineers in constant development and improvement of layout verification tools and methodologies. The purpose of this article is to present methodology and new challenges in layout verification and reliability checks of todays microprocessor layout designs.
Microprocessor Design; Post-Layout Verification; LVS; DRC; Parasitic Extraction; Reduction; Reliability
Razvojem virtualizacijskih tehnologija raste kompleksnost IT sustava, dok korisnici istovremeno zahtijevaju brži pristup resursima, napredne integracije i jednostavnost korištenja. Jedno od ključnih rješenja za ove izazove primjena je…
Ovaj rad istražuje i uspoređuje mogućnosti prosljeđivanja grafičkih kartica na Hyper-V i KVM hipervizorima prema virtualnim strojevima, detaljno opisujući metode, postupke i razlike u arhitekturi koje utječu na…
The ever-growing usage and adaptation of HTTP/3 in web traffic leverages Quick UDP Internet Connections (QUIC) as a transport protocol. QUIC is widely recognized for reduced latency, enhanced…
